The present invention relates generally to integrated circuits, and more specifically to integrated circuits having biased transistor bodies.
Variations in transistor performance occur for a variety of reasons, including statistical variations in manufacturing processes. Variations can exist between transistors in separate integrated circuit dies, as well as between transistors on the same integrated circuit die. One such variation occurs in the threshold voltage of transistors. Threshold voltage (Vt) is the gate voltage at which a transistor turns on. If an integrated circuit design has a nominal Vt, some transistors will exhibit a Vt higher than the nominal Vt, and some transistors will exhibit a Vt lower than the nominal Vt. When Vt is high, the transistor is slower to turn on and leakage currents are low when: the transistor is off. When Vt is low, the transistor is faster to turn on and leakage currents are higher when the transistor is off.
A wide variation in Vt between different integrated circuit dies can cause some parts from a manufacturing run to fail a minimum operating frequency test, while other parts from the same manufacturing run pass the minimum operating frequency test. For example, from a single manufacturing run, some parts may be rated to operate at a frequency of 900 Megahertz (MHZ), while others may be rated to operate at 1 Gigahertz (GHz). It may be that parts capable of functioning at 1 GHz are more profitable, and so parts rated at 900 MHZ produce less profit.
Variations in Vt can also needlessly waste power. It may be that some parts rated to operate at 1 GHz can actually run at 1.1 GHz because of low Vt across critical portions of the circuit. The part may be rated at 1 GHz, and the excess capability is not utilized. Along with the excess speed capability, low Vt can cause an increase in leakage currents. When Vt is lower than necessary, the leakage currents are higher than necessary, resulting in wasted power.
Transistor Vt can also change over time as a result of time varying phenomena such as hot carrier degradation. An integrated circuit die that operates just over 1 GHz may be characterized as a 900 MHZ part to take into account the changing Vt over the life of the integrated circuit. An inability to modify Vt during the life of the integrated circuit can cause devices to be rated below their actual capability when fabricated. This costs manufacturers money.
Various: approaches have been attempted to mitigate the aforementioned problems. Miyazaki utilizes a reverse biasing technique to xe2x80x9csqueezexe2x80x9d the distribution of device delays. See M. Miyazaki et al., xe2x80x9cA Delay Distribution Squeezing Scheme with Speed-Adaptive Threshold-Voltage CMOS (SA-Vt CMOS) for Low Voltage LSIs,xe2x80x9d 1998 International Symposium on Low Power Electronics and Design Proceedings, pp. 48-53, 1998. Kao utilizes Dual Gate Silicon On Insulator technologies for biasing circuits. See J. Kao, xe2x80x9cSOIAS For Temperature and Process Control,xe2x80x9d Massachusetts Institute of Technology, 6.374 Project, December 1996.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for reducing variations in threshold voltages of transistors.
In one embodiment, a method of biasing the body of a transistor, includes measuring a parameter of the transistor, and responsive to the parameter, forward biasing the body of the transistor. The parameter being measured can be, among other things, a voltage threshold of the transistor, or a delay characteristic of the transistor.
In another embodiment, a method of biasing a compensated circuit includes measuring a delay in a matched circuit, the matched circuit including a replica of a signal path within the compensated circuit, and comparing the delay with a predetermined delay to generate a bias value. The method further includes biasing the matched circuit and the compensated circuit in response to the bias value.
In another embodiment, a method of delay matching includes partitioning an integrated circuit into a plurality of blocks capable of being independently biased and measuring characteristic circuit delays within each of the plurality of blocks. The method further includes independently biasing each of the plurality of blocks in response to the characteristic circuit delays within each of the plurality of blocks.
In another embodiment, an adaptive bias generator includes a matched circuit having a clock input node, a clock output node, and a bias input node. The adaptive bias generator further includes a phase comparator having a first input node coupled to the clock output node of the matched circuit, a second input node coupled to the clock input node of the matched circuit, and an output node, and also further includes a digital-to-analog converter responsive to an error value on the output node of the phase comparator, the analog to digital converter having an output node coupled to the bias input node of the matched circuit.
In another embodiment, an integrated circuit includes at least one circuit block, the at least one circuit block comprising at least one transistor disposed within a well, the well having a bias input node, and an adaptive bias generator for each of the at least one circuit block, the adaptive bias generator being configured to provide a voltage value on the bias input node responsive to a measured parameter.